A 1000 frames/s Vision Chip Using Scalable Pixel-Neighborhood-Level Parallel Processing
Document Type
Article
Publication Date
10-2016
Journal Title
IEEE Journal of Solid-State Circuits
Volume
52
Issue
2
Abstract
This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel processing. In the architecture, an 8-b RISC processing core is embedded in an 8×8 array of digital pixel sensors on the same focal plane. These neighborhood processors (NPs) are tiled in a 2-D array to form the final imager resolution. Program execution is carried out in parallel across the array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution, without reduction in processing speed or frame rate. To accomplish this, a compact, low-complexity NP architecture along with a general purpose, 8-b instruction set has been designed and implemented. A prototype vision chip containing an 8×10 array of NPs with a 64×80 resolution has been designed and fabricated in a 0.13-μm 1P8M CMOS fabrication process. The system is reprogrammable and can perform a wide range of image and video processing tasks. Several example algorithms are implemented and tested on the single-chip vision system to demonstrate the functionality of pixel-neighborhood-level parallelism, including 1000-frames/s object tracking.
Recommended Citation
Schmitz, J., Gharzai, M., Balkir, S., Hoffman, M., White, D., and Schemm, N. (2016). A 1000 frames/s vision chip using scalable pixel-neighborhood-level parallel processing. IEEE Journal of Solid-State Circuits, 52(2), 556-568. doi: 10.1109/JSSC.2016.2613094
