Level of Education of Students Involved
Undergraduate
Faculty Sponsor
Dan White
College
College of Engineering (COE)
Discipline(s)
Computer Engineering
ORCID Identifier(s)
0009-0002-7497-5903
Presentation Type
Poster Presentation
Symposium Date
Spring 2025
Abstract
The purpose of this project is to research, test, design, and fabricate a custom microchip. The focus is on CMOS VLSI with an emphasis on digital logic design, design methodology, and testing techniques. The microchip is designed using Verilog and simulated using a suite of tools and testbenches such as Cocotb, GTKWave, and Icarus Verilog. Once verified, the design is submitted to Tiny Tapeout for fabrication.
The chip functions as a base-60 binary clock that displays time in a 12-hour format using 16 LEDs. The time can be set using a switch and a few control buttons, allowing it to be synchronized with the real-world time. This project demonstrates the full workflow from digital design to physical chip fabrication, with a key objective of validating the design before production.
The expected outcome is a functional, fabricated microchip that successfully implements the binary clock design. Through this work, insights are gained into the design process of ASICs, from an HDL to real-world hardware. This research contributes to the understanding of digital design and chip prototyping methods.
Recommended Citation
Gring, Xander, "130nm Chip Design" (2025). Symposium on Undergraduate Research and Creative Expression (SOURCE). 1480.
https://scholar.valpo.edu/cus/1480
poster
Biographical Information about Author(s)
I am a senior computer engineering student with a strong interest in digital logic design, programming, and microcontrollers. My experience includes working with HDLs such as VHDL and Verilog, FPGAs, and various microcontrollers such as Raspberry Pi, Arduino, and STM. This project was inspired by my desire to see my own design fabricated on a chip and to gain hands-on experience using an HDL for chip development, rather than just implementing it on an FPGA.