A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale
di/dt and IR events may cause large supply voltage variations and ohmic losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce ohmic loss. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced that reduces the supply voltage variation magnitude by more than 66% or the future ohmic loss by more than 27% (compared to today's power delivery and decoupling networks) using conventional processing and packaging techniques.
Budnik, Mark M. and Kaushik, Roy, "A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale" (2006). Engineering Faculty Publications & Patents. Paper 19.